How do semiconductor giants collaborate on next-gen memory chips?
Soaring technical demands from AI hardware leaders like Nvidia are forcing rival foundries and memory makers into unexpected manufacturing alliances.
Semiconductor rivals collaborate on next-generation memory chips by dividing production steps based on specialised technical capabilities rather than relying on a single firm's manufacturing line. For Nvidia's custom high-bandwidth memory (NVHBM), memory makers including Samsung use Taiwan Semiconductor Manufacturing Company's (TSMC) advanced 3-nanometre process to build the underlying base dies, while producing upper memory layers in-house. Nvidia enforced this shared standard across Samsung, SK Hynix, and Micron to standardise performance and lower technical verification hurdles across its AI hardware platforms. Meanwhile, chip designers like Broadcom build long-term foundry alliances with Samsung to secure competitive pricing and alternative production capacity.
- Over $200 billion through 2030
- CNBC and Samsung Electronics, July 2026
- TSMC 3-nanometre process
- Seoul Economic Daily, 2026
- $16.5 billion
- CNBC, July 2026
- Sixth-generation DRAM
- The News International, 2026
- Sub-2-nanometre foundry process
- TelecomLead and Samsung Electronics, July 2026
What's happening now
In mid-2026, the artificial intelligence chip market pushed traditional rivals into an unexpected alliance: Samsung Electronics agreed to use TSMC's 3-nanometre manufacturing process to produce base dies for Nvidia's custom high-bandwidth memory chips. Historically, Samsung operated a turnkey model, manufacturing both the core memory layers and the underlying base dies on its own production lines.
The strategic shift follows technical requirements set by Nvidia for its custom NVHBM memory lineup. To standardise memory implementation across suppliers, Nvidia requested that all primary memory partners—Samsung, SK Hynix, and Micron Technology—use TSMC's 3nm process for the base dies, alongside sixth-generation DRAM technology for the core memory dies. Samsung accepted Nvidia's terms to secure its position in Nvidia's supply chain, though it maintains its independent foundry processes for standard high-bandwidth memory products.
At the same time, custom AI chip competition is expanding beyond general-purpose GPUs. On 25 July 2026, Samsung signed a memorandum of understanding with Broadcom envisaged to exceed $200 billion through 2030. The agreement covers high-bandwidth memory supply, sub-2-nanometre contract chip making, and 2.3D and 2.5D advanced packaging for Broadcom's custom AI accelerators.
Media reports on 4 October 2026 showed that Broadcom subsequently locked in chip-pricing terms with Samsung that match the rates Nvidia commands from its memory suppliers. This pricing arrangement gives Broadcom the supply chain leverage required to scale its custom tensor processing unit (TPU) offerings against market leader Nvidia.
How custom high-bandwidth memory chips are built collaboratively
Base die manufacturing at TSMC
TSMC manufactures the underlying logic base die using its 3-nanometre process node. This base die incorporates a custom memory controller built to Nvidia's specifications, providing a uniform physical interface for memory controllers.
Core DRAM fabrication by memory suppliers
Samsung, SK Hynix, or Micron fabricates the core memory layers using sixth-generation DRAM technology. These layers hold the dense memory cells needed to buffer high-speed AI computing data.
Vertical stacking and through-silicon via bonding
Engineers stack the DRAM layers vertically directly on top of TSMC's manufactured base die. Microscopic vertical wire channels, known as through-silicon vias, connect the stacked memory layers to allow fast, direct data transfer.
Advanced packaging alongside the main AI processor
The completed NVHBM stack is mounted on a silicon interposer right beside Nvidia's main AI processor using advanced packaging technology. Placing memory millimetres away from logic reduces latency and power consumption.
Who it affects
In India, where technology firms and cloud providers are expanding data centre infrastructure to run generative AI models, semiconductor supply chain stability directly affects hardware costs and server deployment schedules. Because India imports virtually all of its high-performance computing hardware, supply arrangements between major foundries dictate how quickly local data centres can procure AI accelerators.
Globally, this collaborative model alters business strategies across hardware design, custom silicon development, and contract manufacturing. Hyperscalers developing custom chips rely on foundry choices outside TSMC to lower costs and secure production slots. Partnerships like the Samsung-Broadcom arrangement allow custom ASIC designers to offer tech companies scalable alternatives to standard graphics processors.
What's being done, and is it working
Institution
Nvidia
Mandated a unified base-die manufacturing standard across Samsung, SK Hynix, and Micron using TSMC's 3nm process node.
Market
Samsung Electronics
Adopted a hybrid model using TSMC processes for custom NVHBM base dies while signing a $200 billion partnership with Broadcom through 2030.
Market
Broadcom
Secured a sub-2nm foundry and packaging agreement with Samsung and matched Nvidia's memory pricing terms.
What you can do
Track foundry production roadmaps when planning hardware procurement schedules for AI workloads.
Evaluate whether custom ASIC accelerators or general-purpose GPUs best fit your infrastructure budget.
Monitor high-bandwidth memory packaging standards to ensure hardware compatibility across server nodes.
What we still don't know
- Whether TSMC's 3-nanometre and advanced packaging capacity will be sufficient to supply Nvidia, Apple, and rival designers simultaneously.
- Whether Samsung's sub-2-nanometre process can achieve yield rates high enough to win non-memory chip orders away from TSMC.
Questions readers ask
Why is Samsung using TSMC to make base dies for Nvidia chips?
Nvidia required a unified manufacturing standard across all memory vendors for its custom NVHBM memory chips. To lower verification hurdles and ensure uniform performance, Nvidia asked Samsung, SK Hynix, and Micron to produce their base dies using TSMC's 3-nanometre process node.
What is high-bandwidth memory and why is it essential for AI?
High-bandwidth memory stacks multiple DRAM memory layers vertically, placing them right next to the main processor. This drastically reduces the physical distance data must travel, delivering the speed and bandwidth required for demanding artificial intelligence calculations.
How does the Broadcom-Samsung partnership challenge TSMC?
The $200 billion agreement through 2030 covers sub-2-nanometre chip manufacturing, memory supply, and advanced packaging. By bundling these services together and matching Nvidia's chip pricing terms, Samsung and Broadcom offer technology firms a competitive alternative to TSMC's foundry dominance.
