The India Decade

India scales up chip ambitions with Semicon 2.0 targeting 200 startups and 100,000 technicians

Union Minister Ashwini Vaishnaw announces an expanded scheme focusing on supply chains, applied research, and factory-floor talent.

By The India Decade

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cleanroom technicians working on semiconductor wafers (file image)
cleanroom technicians working on semiconductor wafers (file image) · “Detector testing cleanroom” by Sbaletsk (CC BY 4.0) via Wikimedia Commons

India will target at least 200 chip-design startups and train 100,000 factory-floor technicians under an expanded national semiconductor programme, Union Minister Ashwini Vaishnaw announced on Thursday.

Speaking at the Semicon India 2026 exhibition in New Delhi, Vaishnaw said the next phase of the state-backed initiative, dubbed Semicon 2.0, will build on a first phase that saw 105 startups participate, 20 of which raised Rs 800 crore in venture capital.

"But that was just the beginning," Vaishnaw told the conference at the Yashobhoomi convention centre. "This time, our ambition is much bigger."

The expanded scheme, which received cabinet approval in July with a budget of Rs 1.275 lakh crore, marks a shift in India's strategy. Instead of focusing almost exclusively on attracting multi-billion-dollar fabrication plants, or fabs, the government is trying to build a self-sustaining domestic ecosystem.

Inside the six pillars

The strategy is structured around six core pillars. While the first targets chip-design startups, the second focuses on the heavy machinery, chemicals, and gases needed to run semiconductor lines. Vaishnaw said a newly announced $5 billion investment in this area would help create local jobs.

Other pillars cover physical manufacturing, from traditional silicon wafer fabs to advanced packaging facilities. Vaishnaw pointed to Odisha, where a 3D packaging plant is already under construction, as proof of progress.

The fifth pillar will fund applied research and development, which the minister said would be "fully driven by the industry and academia, absolutely working in harmony".

Training the clean-room workforce

The final pillar tackles the industry's looming labour shortage. While the first phase focused on training high-level design engineers — placing electronic design automation software from firms like Cadence, Siemens, and Synopsys into more than 400 universities — the second phase turns its attention to the factory floor.

The government now wants to build a pipeline of 100,000 technicians skilled in clean-room operations and machinery maintenance. These workers will feed the domestic factories currently under construction, with some expected to join the global workforce.

There is some dispute over how quickly the previous talent targets were met. Vaishnaw noted that Semicon 1.0 set out to train 85,000 design engineers over a decade. He told attendees that 70,000 had already been trained in four years, though government statements in August claimed the full 85,000 target had already been surpassed, with plans now underway to train another 100,000.

The three-day New Delhi summit, organised by the India Semiconductor Mission and global industry association SEMI, has drawn more than 600 exhibitors from 40 countries, highlighting India's growing prominence in the global tech supply chain. Twelve semiconductor projects were approved under the first phase of the national plan, and three have already begun commercial production.

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Key numbers

Semicon 2.0 budget
Rs 1.275 lakh crore
Source: Union Cabinet approval
Target chip-design startups
At least 200
Source: Ashwini Vaishnaw
Target clean-room technicians
100,000
Source: Ashwini Vaishnaw
Venture capital raised in Phase 1.0
Rs 800 crore
Source: Ashwini Vaishnaw
Startups backed by VC in Phase 1.0
20
Source: Ashwini Vaishnaw
Total startups participating in Phase 1.0
105
Source: Ashwini Vaishnaw
Approved semiconductor projects in Phase 1.0
12
Source: Indian Government
Projects in commercial production
3
Source: Indian Government

In this story

  • Ashwini Vaishnaw — India's Union Minister for Electronics and IT who announced the Semicon 2.0 targets.

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